From Wikipedia, the free encyclopedia
The Athlon 64 is an eighth-generation, -architecture
produced by , released on September 23, 2003. It is the third processor to bear the name , and the immediate successor to the . The second processor (after the ) to implement AMD64 architecture and the first
processor targeted at the average consumer, it was AMD's primary consumer microprocessor, and competes primarily with 's , especially the "Prescott" and "Cedar Mill" core revisions. It is AMD's first , eighth-generation processor core for desktop and mobile computers. Despite being natively 64-bit, the AMD64 architecture is backward-compatible with 32-bit
instructions. Athlon 64s have been produced for , ,
and . The line was succeeded by the dual-core
The K8 architecture
The Athlon 64 was originally codenamed ClawHammer by AMD, and was referred to as such internally and in press releases. The first Athlon 64 FX was based on the first
core, SledgeHammer. Both cores, produced on a 130
process, were first introduced on September 23, 2003. The models first available were the FX-51, fitting Socket 940, and the 3200+, fitting Socket 754. Like the Opteron, on which it was based, the Athlon FX-51 required buffered , increasing the final cost of an upgrade. The week of the Athlon 64's launch, Intel released the
Extreme Edition, a CPU designed to compete with the Athlon 64 FX. The Extreme Edition was widely considered a marketing ploy to draw publicity away from AMD, and was quickly nicknamed among some circles the "Emergency Edition". Despite a very strong demand for the chip, AMD experienced early manufacturing difficulties that made it difficult to deliver Athlon 64s in quantity. In the early months of the Athlon 64 lifespan, AMD could only produce 100,000 chips per month. However, it was very competitive in terms of performance to the Pentium 4, with magazine
calling it the "fastest yet". "Newcastle" was released soon after ClawHammer, with half the Level 2 .
Athlon 64 3000+ (2.0 GHz) Newcastle, Socket 754
All the 64-bit processors sold by AMD so far have their genesis in the K8 or Hammer project. On June 1, 2004, AMD released new versions of both the ClawHammer and Newcastle core revisions for the newly introduced , an altered
without the need for buffered memory. Socket 939 offered two main improvements over Socket 754: the
was altered with , doubling peak memory bandwidth, and the
bus was increased in speed from 800 MHz to ;MHz. Socket 939 also was introduced in the FX series in the form of the FX-55. At the same time, AMD also began to ship the "Winchester" core, based on a 90 nanometer process.
Core revisions "Venice" and "San Diego" succeeded all previous revisions on April 15, 2005. Venice, the lower-end part, was produced for both Sockets 754 and 939, and included 512  of L2 cache. San Diego, the higher-end chip, was produced only for Socket 939 and doubled Venice's L2 cache to 1 . Both were produced on the 90 nm fabrication process. Both also included support for the
instruction set, a new feature that had been included in the rival
since the release of the Prescott core in February 2004. In addition, AMD overhauled the memory controller for this revision, resulting in performance improvements as well as support for newer DDR RAM.
On April 21, 2005, less than a week after the release of Venice and San Diego, AMD announced its next addition to the Athlon 64 line, the . Released on May 31, 2005, it also initially had two different core revisions available to the public, Manchester and Toledo, the only appreciable difference between them being the amount of L2 cache. Both were released only for Socket 939. The Athlon 64 X2 was received very well by reviewers and the general public, with a general consensus emerging that AMD's implementation of
was superior to that of the competing . Some felt initially that the X2 would cause market confusion with regard to price points since the new processor was targeted at the same "enthusiast," US$350 and above market already occupied by AMD's existing socket 939 Athlon 64s. AMD's official breakdown of the chips placed the Athlon X2 aimed at a segment they called the "prosumer", along with digital media fans. The Athlon 64 was targeted at the mainstream consumer, and the Athlon FX at gamers. The
budget processor was targeted at value-conscious consumers. Following the launch of the Athlon 64 X2, AMD surpassed Intel in US retail sales for a period of time, although Intel retained overall market leadership because of its exclusive relationships with direct sellers such as Dell.
The Athlon 64 had been maligned by some critics for some time because of its lack of support for , an emerging technology that had been adopted much earlier by Intel. AMD's official position was that the
on DDR2 had not progressed to a point where it would be advantageous for the consumer to adopt it. AMD finally remedied this gap with the "Orleans" core revision, the first Athlon 64 to fit , released on May 23, 2006. "Windsor", an Athlon 64 X2 revision for Socket AM2, was released concurrently. Both Orleans and Windsor have either 512
of L2 cache per core. The Athlon 64 FX-62 was also released concurrently on the Socket AM2 platform. Socket AM2 also consumes less power than previous platforms, and supports .
The memory controller used in all DDR2 SDRAM capable processors (Socket AM2), has extended column address range of 11 columns instead of conventional 10 columns, and the support of 16 KB page size, with at most 2048 individual entries supported. An
unbuffered DDR2 kit, optimized for
, was released to exploit the functionality provided by the memory controller in socket AM2 processors, allowing the memory controller to stay longer on the same page, thus benefitting graphics intensive applications.
The Athlon architecture was further extended with the release of Athlon Neo processors on January 9, 2009. Based on the same architecture as the other Athlon 64 variants, the new processor features a small package footprint targeting
AMD Athlon 64 processor family
Code-named
Date released
Code-named
Date released
ClawHammer
Winchester
Manchester *
130 nm
130 nm
90 nm
90 nm
90 nm
90 nm
90 nm
April 2005
ClawHammer
130 nm
130 nm
90 nm
90 nm
SledgeHammer
ClawHammer
130 nm
130 nm
90 nm
65 nm
65 nm
65 nm
with one core disabled
There are four variants: Athlon 64, Athlon 64 FX, Mobile Athlon 64 (later renamed "") and the dual-core . Common among the Athlon 64 line are a variety of instruction sets including , , , , and . All Athlon 64s also support the , a security feature named "Enhanced Virus Protection" by AMD. And as implementations of the AMD64 architecture, all Athlon 64 variants are able to run , 32 bit , and
, through two different modes the processor can run in: "" and "long mode". Legacy mode runs 16-bit and 32-bit programs natively, and long mode runs 64-bit programs natively, but also allows for 32-bit programs running inside a 64-bit . All Athlon 64 processors feature 128  of level 1 cache, and at least 512 KB of level 2 cache.
The Athlon 64 features an on-die memory controller, a feature previously seen on only the . Not only does this mean the controller runs at the same clock rate as the CPU itself, it also means the electrical signals have a shorter physical distance to travel compared to the old
interfaces. The result is a significant reduction in latency (response time) for access requests to main memory. The lower latency was often cited as one of the advantages of the Athlon 64's architecture over those of its competitors at the time.
As the memory controller is integrated onto the CPU die, there is no FSB for the system memory to base its speed upon. Instead, system memory speed is obtained by using the following formula (using the ):
{\displaystyle {\frac {\mathrm {CPU~speed} }{\left\lceil {\frac {\mathrm {CPU~multiplier} }{\mathrm {DRAM~divider} }}\right\rceil }}=\mathrm {DRAM~speed} }
In simpler terms, the memory is always running at a set fraction of the CPU speed, with the divisor being a whole number. A 'FSB' figure is still used to determine the CPU speed, but the RAM speed is no longer directly related to this 'FSB' figure (known otherwise as the LDT).
A second bus, the northbridge, connected the CPU to the chipset and device attachment bus (PCIe, AGP, PCI). This was implemented using a new high-performance standard, . AMD attempted, with some success, to make this an industry standard. It was also useful in building multi-processor systems without additional glue chips.
(TLBs) have also been enlarged (40 4k/2M/4M entries in L1 cache, 512 4k entries), with reduced latencies and improved branch prediction, with four times the number of bimodal counters in the global history counter. This and other architectural enhancements, especially as regards SSE implementation, improve instruction per cycle () performance over the previous Athlon XP generation. To make this easier for consumers to understand, AMD has chosen to market the Athlon 64 using a
(Performance Rating) system, where the numbers roughly map to Pentium 4 performance equivalents, rather than actual clock speed.
Athlon 64 also features
speed throttling technology branded , a feature similar to Intel's
that can throttle the processor's clock speed back to facilitate lower power consumption and heat production. When the user is running undemanding applications and the load on the processor is light, the processor's clock speed and voltage are reduced. This in turn reduces its peak power consumption (max TDP set at 89 W by AMD) to as low as 32 W ( C0, clock speed reduced to 800 MHz) or 22W (stepping CG, clock speed reduced to 1 GHz). The Athlon 64 also has an
(IHS) which prevents the CPU die from accidentally being damaged when mounting and unmounting heat sinks. With prior AMD CPUs a
could be used by people worried about damaging the die.
supported by
Service Pack 2 and future versions of Windows,
2.6.8 and higher and
5.3 and higher is also included, for improved protection from malicious buffer overflow security threats. Hardware-set permission levels make it much more difficult for malicious code to take control of the system. It is intended to make
a more secure environment.
The Athlon 64 CPUs have been produced with 130 nm and 90 nm
process technologies. All of the latest chips (Winchester, Venice and San Diego models) are on 90 nm. The Venice and San Diego models also incorporate dual stress liner technology (an amalgam of
and 'squeezed silicon', the latter of which is not actually a technology) co-developed with IBM.
The Athlon 64 FX is positioned as a hardware enthusiast product, marketed by AMD especially toward . Unlike the standard Athlon 64, all of the Athlon 64 FX processors have their multipliers completely unlocked. Starting with the FX-60, the FX line became dual-core.
The FX always has the highest clock speed of all Athlons at its release. From FX-70 onwards, the line of processors will also support dual-processor setup with , named .
The Athlon 64 X2 is the first
manufactured by . In 2007, AMD released two final Athlon 64 X2 versions: the AMD Athlon 64 X2 6400+ and 5000+ Black Editions. Both processors feature an unlocked multiplier, which allows for a large range of overclocked settings. The 6400+ is based on a 90 nm Windsor core (3.2 GHz, 2x1MB L2, 125W TDP) while the 5000+ is based on a 65 nm Brisbane core (2.6 GHz, 2x512KB L2, 65W TDP). These Black Edition processors are available at retail, but AMD does not include heatsinks in the retail package.
Model MT-34
MT-34 (bottom)
Previously introduced as "Mobile Athlon 64", Turion 64 is now the
applies to its 64-bit low-power consumption (mobile) . The
processors compete with 's mobile processors, initially the
and later the
processors.
Earlier Turion 64 processors are compatible with AMD's . The newer "Richmond" models are designed for AMD's . They are equipped with 512 or ; of L2 cache, a 64-bit single channel on-die memory controller, and an 800 MHz
bus. Battery saving features, like , are central to the marketing and usefulness of these CPUs.
The model naming scheme does not make it obvious how to compare one Turion with another, or even an Athlon 64. The model name is two letters, a dash, and a two digit number (for example, ML-34). The two letters together designate a processor class, while the number represents a . The first letter is M for single core processors and T for dual core
processors. The later in the alphabet that the second letter appears, the more the model has been designed for mobility (frugal power consumption). Take for instance, an MT-30 and an ML-34. Since the T in the MT-30 is later in the alphabet than the L in ML-34, the MT-30 consumes less power than the ML-34. But since 34 is greater than 30, the ML-34 is faster than the MT-30.
With 27 mm × 27 mm in size and 2.5 mm in thickness, the Athlon Neo processors utilize a new package called "ASB1", essentially a
package, for smaller footprint to allow smaller designs for notebooks and lowering the cost. The clock of the processors is significantly lower than desktop and other mobile counterparts to reach a low TDP, at 15W maximum for a single core x86-64 CPU at 1.6 GHz. The Athlon Neo processors are equipped with 512 KB of L2 cache and HyperTransport 1.0 running at 800 MHz frequency.
: The Athlon 64 value/budget line, 64-bit memory interface (Single-Channel)
: Athlon 64 performance line, , and newer Athlon 64 FXs, , 128-bit memory interface ()
and old Athlon 64 FX, 128-bit memory interface - requires registered DDR memory
: Athlon 64/Athlon 64 FX/Athlon 64 X2/, 940 Pins (Not compatible with Socket 940); the first AMD socket to use .
: Opteron, 1207 Pins
: Athlon 64 FX on , also compatible for dual-processor
2200 series
At the introduction of Athlon 64 in September 2003, only Socket 754 and Socket 940 (Opteron) were ready and available. The onboard memory controller was not capable of running unbuffered (non-registered) memory in dual-channel mode at as a stopgap measure, they introduced the Athlon 64 on Socket 754, and brought out a non-multiprocessor version of the Opteron called the Athlon 64 FX, as a multiplier unlocked enthusiast part for Socket 940, comparable to Intel's Pentium 4 Extreme Edition for the high end market.
In June 2004, AMD released Socket 939 as the mainstream Athlon 64 with dual-channel memory interface, leaving Socket 940 solely for the server market (Opterons), and relegating Socket 754 as a value/budget line, for Semprons and slower versions of the Athlon 64. Eventually Socket 754 replaced
for Semprons.
In May 2006, AMD released Socket AM2, which provided support for the DDR2 memory interface. Also, this marked the release of .
In August 2006, AMD released Socket F for
server CPU which uses the
chip form factor.
In November 2006, AMD released a specialized version of Socket F, called 1207 FX, for dual-socket, dual-core Athlon FX processors on the Quad FX platform. While Socket F Opterons already allowed for four processor cores, Quad FX allowed unbuffered RAM and expanded CPU/chipset configuration in the BIOS. Consequentially, Socket F and F 1207 FX are incompatible and require different processors, chipsets, and motherboards.
CPU-Stepping: C0, CG
L1-Cache: 64 + 64 KB (Data + Instructions)
L2-Cache: 1024 KB, fullspeed
, Extended , , ,
, 800 MHz
Registered DDR-SDRAM required
VCore: 1.50/1.55 V
Power Consumption (): 89 Watt max
First Release: September 23, 2003
Clockrate: ;MHz (FX-51, C0), ;MHz (FX-53, C0 and CG)
CPU-Stepping: CG
L1-Cache: 64 + 64 KB (Data + Instructions)
L2-Cache: 1024 KB, fullspeed
, Extended , , ,
VCore: 1.50 V
Power Consumption (): 89 Watt (FX-55:104 Watt)
First Release: June 1, 2004
Clockrate: ;MHz (FX-53), ;MHz (FX-55)
CPU-Stepping: E4, E6
L1-Cache: 64 + 64 KB (Data + Instructions)
L2-Cache: 1024 KB, fullspeed
, Extended , , , , , ,
VCore: 1.35 V or 1.40 V
Power Consumption (): 104 Watt max
First Release: April 15, 2005
Clockrate: ;MHz (FX-55), ;MHz (FX-57)
Dual-core CPU
CPU-Stepping: E6
L1-Cache: 64 + 64 KB (Data + Instructions), per core
L2-Cache: 1024 KB fullspeed, per core
, Extended , , , , , ,
VCore: 1.30 V - 1.35 V
Power Consumption (): 110 Watt max
First Release: January 10, 2006
Clockrate: ;MHz (FX-60)
Dual-core CPU
CPU-Stepping: F2, F3
L1-Cache: 64 + 64 KB (Data + Instructions), per core
L2-Cache: 512 - 1024 KB fullspeed, per core
, Extended , , , , , , ,
VCore: 1.30 V - 1.40 V
Power Consumption (): 125 Watt max
First Release: May 23, 2006
Clockrate: ;- ;MHz (6400+), ;MHz (FX-62)
Dual-core, dual CPUs (four cores total)
CPU-Stepping: F3
L1-Cache: 64 + 64 KB (Data + Instructions), per core
L2-Cache: 1024 KB fullspeed, per core
, Extended , , , , , , ,
VCore: 1.35 V - 1.40 V
Power Consumption (): 125 Watt max per CPU
First Release: November 30, 2006
Clockrate: ;MHz (FX-70), ;MHz (FX-72), ;MHz (FX-74)
CPU-Stepping: C0, CG
L1-Cache: 64 + 64 KB (Data + Instructions)
L2-Cache: 1024 KB, fullspeed
, Extended , , , , ,
, 800 MHz
VCore: 1.50 V
Power Consumption (): 89 Watt max
First Release: September 23, 2003
Clockrate:  MHz
Also possible: ClawHammer-512 (Clawhammer with partially disabled L2-Cache)
CPU-Stepping: CG
L1-Cache: 64 + 64 KB (Data + Instructions)
L2-Cache: 512 KB, fullspeed
, Extended , , , , ,
, 800 MHz
VCore: 1.50 V
Power Consumption (): 89 Watt max
First Release: 2004
Clockrate:  MHz
CPU-Stepping: D0
L1-Cache: 64 + 64 KB (Data + Instructions)
L2-Cache: 512 KB, fullspeed
, Extended , , , , ,
VCore: 1.40 V
Power Consumption (): 67 Watt max
First Release: 2004
Clockrate:  MHz
CPU-Stepping: E3, E6
L1-Cache: 64 + 64 KB (Data + Instructions)
L2-Cache: 512 KB, fullspeed
, Extended , , , , , ,
, 800 MHz
VCore: 1.35 V or 1.40 V
Power Consumption (): 89 Watt max
First Release: April 4, 2005
Clockrate:  MHz
CPU-Stepping: E4, E6
L1-Cache: 64 + 64 KB (Data + Instructions)
L2-Cache: 1024 KB, fullspeed
, Extended , , , , , ,
VCore: 1.35 V or 1.40 V
Power Consumption (): 89 Watt max
First Release: April 15, 2005
Clockrate:  MHz
CPU-Stepping: F1
L1-Cache: 2 x 64 + 2 x 64 KB (Data + Instructions)
L2-Cache: 2 x 512 KB, fullspeed
, Extended , , , , , ,
VCore: 1.35 V
Power Consumption (): 89 Watt max
First Release: April 15, 2005
Clockrate:  MHz
CPU-Stepping: F2, F3
L1-Cache: 64 + 64 KB (Data + Instructions)
L2-Cache: 512 KB, 1M
, Extended , , , , , , ,
VCore: 1.25 V or 1.40 V
Power Consumption (): 62 Watt max
First Release: May 23, 2006
Clockrate:  MHz
CPU-Stepping: G1
L1-Cache: 64 + 64 KB (Data + Instructions)
L2-Cache: 512 KB, fullspeed
, Extended , , , , , , ,
VCore: 1.25/1.35/1.40V
Power Consumption (): 45 Watt max
First Release: February 20, 2007
Clockrate:  MHz
CPU-Stepping: G2
L1-Cache: 64 + 64 KB (Data + Instructions)
L2-Cache: 512 KB, fullspeed
, Extended , , , , , , ,
(), 800 MHz
VCore: 1.1 V
Power Consumption (): 15 Watt max
First Release: January 8, 2009
Clockrate: ;MHz
Generation: K8
65 nm SOI
CPU-Stepping: G
L1-Cache: 64 + 64 KB (Data + Instructions)
L2-Cache: 512 KB, fullspeed
, Extended , , , , , ,
(), 800 MHz
Power Consumption (): 13 Watt max
PowerNow: No
P-States: 1
Clockrate: ;MHz
Generation: K8
65 nm SOI
CPU-Stepping: G
L1-Cache: 64 + 64 KB (Data + Instructions)
L2-Cache: (2*256 KB), fullspeed
, Extended , , , , , (?), ,
(), 800 MHz
Power Consumption (): 18 Watt max
PowerNow: Yes
Clockrate: ;MHz
Generation: K8
65 nm SOI
CPU-Stepping: G2
L1-Cache: 64 + 64 KB (Data + Instructions)
L2-Cache: (2*512 KB), fullspeed
, Extended , , , , , , ,
(), 800 MHz
Power Consumption (): 18 Watt max
PowerNow: Yes
Clockrate: ;MHz
The Athlon 64 was succeeded by the
architecture in 2007, including but not limited to the
processors. These successors feature higher core counts per CPU, and implement Hypertransport 3.0 and Socket AM2+/AM3.
As of February 2012, Athlon64 X2 processors were still available for sale.
Wasson, Scott (). .
from the original on 9 July 2006.
from the original on 7 July 2006.
from the original on 6 July 2006.
Spooner, John (). . CNET.
from the original on 10 June 2006.
from the original on 12 June 2006.
Angelini, C. (). .
De Gelas, Johan (). .
from the original on 8 July 2006.
Shilov, Anton (). .
from the original on 21 May 2006.
Mainelli, Tom (). .
from the original on 18 July 2006.
Lal Shimpi, Anand (). .
from the original on 14 June 2006.
Gavrichenkov, Ilya (). .
from the original on 19 July 2006.
Schmid, P Bert T?pelt (). .
Gavrichenkov, Ilya (). .
from the original on 14 August 2006.
Gavrichenkov, Ilya (). .
from the original on 17 June 2006.
King, Greg (). . Archived from
Wasson, Scott (). .
from the original on 19 June 2006.
Gavrichenkov, Ilya (). .
from the original on 13 August 2006.
from the original on 16 June 2006.
Lal Shimpi, Anand (). .
from the original on 27 June 2006.
Freeman, Vince (). .
from the original on 19 June 2006.
Brown, Rich (). .
Schmid, Patrick (). .
Bennett, Kyle (). .
from the original on 14 June 2006.
Kawamoto, Dawn (). .
Shrout, Ryan (). .
from the original on 9 July 2006.
Shilov, Anton (). .
from the original on 15 July 2006.
Romanchenko, V Sofronov, Dmitry (). .
from the original on 18 July 2006.
Shrout, Ryan (). .
from the original on 9 July 2006.
from the original on 16 June 2006.
from the original on 5 July 2006.
(PDF). June 2004.
(PDF) from the original on 28 June 2006.
Breeden II, John (). . The Washington Post. p. F07.
Tong, Terren (). .
from the original on 14 June 2006.
from the original on 3 June 2006.
PC Magazine
from the original on 19 June 2006.
from the original on 8 July 2006.
from the original on 12 July 2006.
Wasson, Scott (). .
Gavrichenkov, Ilya (). .
from the original on 12 September 2006.
from the original on 21 October 2006.
from the original on 4 July 2006.
Leeth, Tim (). .
from the original on 8 July 2006.
Lal Shimpi, Anand (). .
from the original on 7 July 2006.
Schmid, P T?pelt, Bert (). .
. Google. .