使用DS12C887时钟芯片设计高精度时钟_百度文库
两大类热门资源免费畅读
续费一年阅读会员，立省24元！
评价文档：
&&¥1.00
&&¥3.00
&&¥2.00
喜欢此文档的还喜欢
使用DS12C887时钟芯片设计高精度时钟
阅读已结束，如果下载本文需要使用
想免费下载本文？
把文档贴到Blog、BBS或个人站等：
普通尺寸(450*500pix)
较大尺寸(630*500pix)
你可能喜欢时钟芯片DS12C887使用说明_百度文库
两大类热门资源免费畅读
续费一年阅读会员，立省24元！
评价文档：
&&¥1.00
喜欢此文档的还喜欢
时钟芯片DS12C887使用说明
阅读已结束，如果下载本文需要使用
想免费下载本文？
把文档贴到Blog、BBS或个人站等：
普通尺寸(450*500pix)
较大尺寸(630*500pix)
你可能喜欢例程_百度文库
两大类热门资源免费畅读
续费一年阅读会员，立省24元！
评价文档：
暂无相关推荐文档
阅读已结束，如果下载本文需要使用
想免费下载本文？
把文档贴到Blog、BBS或个人站等：
普通尺寸(450*500pix)
较大尺寸(630*500pix)
你可能喜欢实时时钟DS12885/DS12887/DS12887A/DS12C887/DS12C887A世纪寄存器（仅DS12C887/DS12C887A）世纪寄存器在位置32H是BCD寄存器设计为自动加载BCD值20为从99到00年内寄存器变化.20时的负荷,就会发生这个寄存器的MSB不受影响,并保持在写的值该用户.读数寄存器C.当时寄存器C被读取,以确保没有中断都将丢失每个使用标志位应进行检查.第二标志位的方法是使用完全启用中断.当一个中断标志位被置位和COR-响应中断使能位也被设置,IRQ引脚低电平.IRQ只要被断言为至少一个三个中断源都有其标志和使能位设置.在寄存器C IRQF位是1的时候IRQ引脚被拉低.认定该RTC发起了一个中断是由读数寄存器C.逻辑实现1在第7位（IRQF位）表示一个或多个中断已经启动的设备.阅读行为寄存器C清除所有的活动标志位及IRQF位.非易失性RAM（非易失RAM）通用非易失RAM字节不是专用于装置内的任何特殊功能.它们可用于由处理器程序作为电池备份存储器和完全可用在更新周期.中断该RTC家族包括三个独立的,完全自动中断的处理器资源.报警中断可以被编程为发生在速率从每秒一次到每天一次.周期性的中断可以选择率从500毫秒到122μs.该updateended中断可用于指示的程序的更新周期完成.每个这些独立的中断条件进行更详细的在该文本的其它部分所述.,该处理器方案可以选择中断,如果有的话,将被使用.三个位在寄存器B启用中断.写一个逻辑1到中断使能位该中断被启动时允许事件发生. A 0的中断使能位禁止IRQ针从该中断条件被断言.如果当一个中断是一个中断标志已设置启用后,IRQ立即设置在一个活跃的水平,虽然中断引发的事故,可能发生较早.因此,在某些情况下程序之前,应先启用新的中断清除较早开始中断.当中断事件发生时,有关标志位为设置在寄存器C.逻辑1这些标志位被置不知疲倦-相应的使能位在该州的吊灯寄存器B.标志位可以在轮询模式下使用不启用相应的允许位.该中断标志位是一个状态位,软件可以interro-必要时门.当一个标志被设置,指示是考虑到已发生中断事件的软件自该标志位是上次读取;但是,应使用该标志位,当它们被清除应采取每次寄存器C被读取.双卡扣INCLUD-教育署与寄存器C使被设置位保持STA-竹叶提取整个读周期.这是将所有的位（高）被清除阅读时,和新的中断是在读周期未决被保持,直到后循环完成.一个,两个或三个位可以被设置18振荡器控制寄存器当DS12887,DS12887A,DS12C887,和DS12C887A是从出厂时,内部振荡器关闭.这可以防止锂能源电池被使用,直到设备被安装在系统中.010位寄存器A的4至6一个模式打开振荡器,使倒计时链.11倍（DV2 = 1,DV1 = 1,DV0 = X）模式打开振荡器,但保持在复位振荡器的倒计时链.位4到6的所有其他组合保持振荡器关闭.方波输出的选择15除法器水龙头十三是提供给一个1
16多路转换器,如图所示的功能框图.方波和周期中断发生器共享多路转换器的输出.该RS0-RS3位寄存器A建立多路复用器的输出频率（见表1）.一旦频率选择,SQW引脚的输出可以开启和关闭程序的控制下与方波使能位,SQWE.周期性中断选择周期性中断原因IRQ针去一个活跃的状态从每500ms每122μs一次一次.这个功能是分开的报警中断,这可以从每秒一次到每天一次输出.周期性中断率是使用相同的选注册是选择方波频率A位（表1）.更改寄存器A位的影响方波的频率和周期性中断输出放.然而,每个函数都有一个单独的使能位寄存器B. SQWE位控制方波输出.同样,在寄存器B的PIE位使周期性的中断.周期性的中断可以用软件计数器用来衡量投入,建立输出间隔,或等待下一个需要的软件功能.____________________________________________________________________
Real-Time ClocksDS12885/DS12887/DS12887A/DS12C887/DS12C887ACentury Register(DS12C887/DS12C887A Only)The century register at location 32h is a BCD registerdesigned to automatically load the BCD value 20 as theyear register changes from 99 to 00. The MSB of thisregister is not affected when the load of 20 occurs, andremains at the value written by the user.when reading Register C. Each used flag bit should beexamined when Register C is read to ensure that nointerrupts are lost.The second flag bit method is used with fully enabledinterrupts. When an interrupt flag bit is set and the cor-responding interrupt-enable bit is also set, theIRQpin isasserted low.IRQis asserted as long as at least one ofthe three interrupt sources has its flag and enable bitsset. The IRQF bit in Register C is a 1 whenever theIRQpin is driven low. Determination that the RTC initiated aninterrupt is accomplished by reading Register C. A logic1 in bit 7 (IRQF bit) indicates that one or more interruptshave been initiated by the device. The act of readingRegister C clears all active flag bits and the IRQF bit.Nonvolatile RAM (NV RAM)The general-purpose NV RAM bytes are not dedicatedto any special function within the device. They can beused by the processor program as battery-backedmemory and are fully available during the update cycle.InterruptsThe RTC family includes three separate, fully automaticsources of interrupt for a processor. The alarm interruptcan be programmed to occur at rates from once persecond to once per day. The periodic interrupt can beselected for rates from 500ms to 122us. The update-ended interrupt can be used to indicate to the programthat an update cycle is complete. Each of these inde-pendent interrupt conditions is described in greaterdetail in other sections of this text.The processor program can select which interrupts, ifany, are to be used. Three bits in Register B enable theinterrupts. Writing a logic 1 to an interrupt-enable bitpermits that interrupt to be initiated when the eventoccurs. A 0 in an interrupt-enable bit prohibits theIRQpin from being asserted from that interrupt condition. Ifan interrupt flag is already set when an interrupt isenabled,IRQis immediately set at an active level,although the interrupt initiating the event may haveoccurred earlier. As a result, there are cases where theprogram should clear such earlier initiated interruptsbefore first enabling new interrupts.When an interrupt event occurs, the relating flag bit isset to logic 1 in Register C. These flag bits are set inde-pendent of the state of the corresponding enable bit inRegister B. The flag bit can be used in a polling modewithout enabling the corresponding enable bits. Theinterrupt flag bit is a status bit that software can interro-gate as necessary. When a flag is set, an indication isgiven to software that an interrupt event has occurredsince the fl however, care shouldbe taken when using the flag bits as they are clearedeach time Register C is read. Double latching is includ-ed with Register C so that bits that are set remain sta-ble throughout the read cycle. All bits that are set (high)are cleared when read, and new interrupts that arepending during the read cycle are held until after thecycle is completed. One, two, or three bits can be set18Oscillator Control BitsWhen the DS12887, DS12887A, DS12C887, andDS12C887A are shipped from the factory, the internaloscillator is turned off. This prevents the lithium energycell from being used until the device is installed in asystem.A pattern of 010 in bits 4 to 6 of Register A turns theoscillator on and enables the countdown chain. A pat-tern of 11x (DV2 = 1, DV1 = 1, DV0 = X) turns the oscil-lator on, but holds the countdown chain of the oscillatorin reset. All other combinations of bits 4 to 6 keep theoscillator off.Square-Wave Output SelectionThirteen of the 15 divider taps are made available to a 1-of-16 multiplexer, as shown in the functional diagram.The square-wave and periodic-interrupt generatorsshare the output of the multiplexer. The RS0–RS3 bits inRegister A establish the output frequency of the multi-plexer (see Table 1). Once the frequency is selected, theoutput of the SQW pin can be turned on and off underprogram control with the square-wave enable bit, SQWE.Periodic Interrupt SelectionThe periodic interrupt causes theIRQpin to go to anactive state from once every 500ms to once every 122us.This function is separate from the alarm interrupt, whichcan be output from once per second to once per day.The periodic interrupt rate is selected using the sameRegister A bits that select the square-wave frequency(Table 1). Changing the Register A bits affects thesquare-wave frequency and the periodic-interrupt out-put. However, each function has a separate enable bit inRegister B. The SQWE bit controls the square-wave out-put. Similarly, the PIE bit in Register B enables the peri-odic interrupt. The periodic interrupt can be used withsoftware counters to measure inputs, create output inter-vals, or await the next needed software function.____________________________________________________________________
搜IC独家提供千万种元器件的中文手册与中文搜索
如果您在这里找不到，那么在其它任何地方更不可能找到
开通DS12C887+中文版PDF下载权限，共22页
已经购买过？&&|&&
正在生成PDF文件，请稍候...
当前进度：
中文版仅供参考，如有出入请
请注意，PDF的下载链接保留3天，付费后请尽快下载。
无法下载PDF？