sch一1939的设备技术参数表表

AD1939 (AD) PDF技术资料下载
AD1939 供应信息 IC Datasheet 数据表 (1/32 页)
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4 ADC / DAC 8与PLL , 192千赫, 24位编解码器
[4 ADC/8 DAC with PLL, 192 kHz, 24-Bit CODEC]
&&AD1939PDF文件:
4 ADC / DAC 8与PLL , 192千赫, 24位编解码器[4 ADC/8 DAC with PLL, 192 kHz, 24-Bit CODEC]
文件大小:&&438 KPDF页数:
&&32 页联系供应商:&& 品牌Logo:
&&&&AD [ ANALOG DEVICES ]
4 ADC/8 DAC with PLL,192 kHz, 24-Bit CODECAD1939FEATURESPLL generated or direct master clockLow EMI design112 dB DAC/107 dB ADC dynamic range and SNR-94 dB THD + NSingle 3.3 V supplyTolerance for 5 V logic inputsSupports 24-bits and 8 kHz to 192 kHz sample ratesDifferential ADC inputDifferential DAC outputLog volume control with autoramp functionSPI(R) controllable for flexibilitySoftware controllable clickless muteSoftware power-downRight-justified, left-justified, I2S, and TDM modesMaster and slave modes up to 16-channel in/out64-lead LQFP packageGENERAL DESCRIPTIONThe AD1939 is a high performance, single-chip codec thatprovides four analog-to-digital converters (ADCs) withdifferential input and eight digital-to-analog converters (DACs)with differential output using the Analog Devices, Inc. patentedmultibit sigma-delta (Σ-Δ) architecture. An SPI port is included,allowing a microcontroller to adjust volume and many otherparameters. The AD1939 operates from 3.3 V digital and analogsupplies. The AD1939 is available in a 64-lead (differentialoutput) LQFP package.The AD1939 is designed for low EMI. This consideration isapparent in both the system and circuit design architectures.By using the on-board PLL to derive the master clock from theLR clock or from an external crystal, the AD1939 eliminatesthe need for a separate high frequency master clock and canalso be used with a suppressed bit clock. The digital-to-analogand analog-to-digital converters are designed using the latestADI continuous time architectures to further minimize EMI.By using 3.3 V supplies, power consumption is minimized,further reducing emissions.APPLICATIONSAutomotive audio systemsHome Theater SystemsSet-top boxesDigital audio effects processorsFUNCTIONAL BLOCK DIAGRAMDIGITAL AUDIOINPUT/OUTPUTAD1939SERIAL DATA PORTDACDACADCANALOGAUDIOINPUTSADCADCADCDIGITALFILTERSDATAOUTSDATAINCLOCKSTIMING MANAGEMENTAND CONTROL(CLOCK AND PLL)DIGITALFILTERANDVOLUMECONTROLDACDACDACDACDACDACPRECISIONVOLTAGEREFERENCECONTROL PORTSPI/I2CANALOGAUDIOOUTPUTSCONTROL DATAINPUT/OUTPUTFigure 1.Rev. 0Information furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or otherrights of third parties that may result from its use. Specifications subject to change without notice. Nolicense is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA , U.S.A.Tel: 781.329.4700Fax: 781.461.3113(C)2006 Analog Devices, Inc. All rights reserved.

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