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时间:2017-05-10 05:08
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C语言密码输入
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用C语言怎么模拟出打字机的效果间断地输出一个电话号码...这是我在写手机通讯录里面遇到的问题
拔号功能:当选中某个姓名时,屏幕上模拟打字机的效果依次显示出此人的电话号码中的各个数字,并伴随相应的拔号声音。
zhoulijun05的答复:
设计原理 计数时钟由模为60的秒计数器模块、模为60的分计数模块、模为24的小时计数器模块、指示灯与报警器的模块、分/小时设定模块及输出显示模块等组成。通过&多功能复用按键F1-F12&信号接线组&F1_12(T)&的F9~F12的任意引线插孔可设置小时和分钟的值,并具有整点报时的功能。&br/&&br/& 输入信号:SETMIN为分钟设置信号;SETHOUR为小时设置信号;RESET为全局复位信号;CLK为全局时钟信号;CKDSP为数码管动态扫描信号。&br/&&br/& 拨码开关SW1~SW7内部已连接并已锁定,无需外接连线。&br/&&br/& 参考源程序 libraryIEEE; useIEEE.std_logic_1164. useieee.std_logic_unsigned. useieee.std_logic_arith. entityxsecondis port( clk:inSTD_LOGIC; clkset:inSTD_LOGIC; setmin:inSTD_LOGIC; reset:inSTD_LOGIC; secout:outSTD_LOGIC_VECTOR(6downto0); enmin:outSTD_LOGIC ); architecturexsecond_archofxsecondis signalsec:std_logic_vector(6downto0); signalemin:std_ signalsec1:std_ begin --&& process(reset,sec,emin,setmin,clkset) begin ifreset='0'then enmin&='0'; secout&=&0000000&; sec1&='1'; else sec1&='0'; secout&= ifclkset='1'andclkset'eventthen ifsetmin='0'then enmin&='1'; else enmin&= process(clk,sec1) aliaslcount:std_logic_vector(3downto0)issec(3downto0); aliashcount:std_logic_vector(2downto0)issec(6downto4); begin ifsec1='1'then sec&=&0000000&; else if(clk='1'andclk'event)then iflcount=9then lcount&=&0000&; ifhcount/=5then hcount&=hcount+1; emin&='0'; else hcount&=&000&; emin&='1'; else lcount&=lcount+1; emin&='0'; endxsecond_ libraryIEEE; useIEEE.std_logic_1164. useieee.std_logic_unsigned. useieee.std_logic_arith. entityxminuteis port( clkmin:inSTD_LOGIC; reset:inSTD_LOGIC; sethour:inSTD_LOGIC; clk:inSTD_LOGIC; minout:outSTD_LOGIC_VECTOR(6downto0); enhour:outSTD_LOGIC ); architecturexminute_archofxminuteis signalmin:std_logic_vector(6downto0); signalehour:std_ signalmin1:std_ begin --&& process(reset,clk,sethour,min,ehour) begin ifreset='0'then enhour&='0'; minout&=&0000000&; min1&='0'; else min1&='1'; minout&= ifclk='1'andclk'eventthen ifsethour='0'then enhour&='1'; else enhour&= process(clkmin,min1) aliaslcountm:std_logic_vector(3downto0)ismin(3downto0); aliashcountm:std_logic_vector(2downto0)ismin(6downto4); begin ifmin1='0'then min&=&0000000&; else if(clkmin='1'andclkmin'event)then iflcountm=9then lcountm&=&0000&; ifhcountm/=5then hcountm&=hcountm+1; ehour&='0'; else hcountm&=&000&; ehour&='1'; else lcountm&=lcountm+1; ehour&='0'; endxminute_ libraryIEEE; useIEEE.std_logic_1164. useieee.std_logic_unsigned. useieee.std_logic_arith. entityxhouris port( clkhour:inSTD_LOGIC; reset:inSTD_LOGIC; hourout:outSTD_LOGIC_VECTOR(5downto0) ); architecturexhour_archofxhouris signalhour:std_logic_vector(5downto0); begin --&& process(reset,clkhour,hour) aliaslcount:std_logic_vector(3downto0)ishour(3downto0); aliashcount:std_logic_vector(1downto0)ishour(5downto4); begin ifreset='0'then hourout&=&000000&; hour&=&000000&; else if(clkhour='1'andclkhour'event)then iflcount=9then lcount&=&0000&; hcount&=hcount+1; else ifhour=&100011&then hour&=&000000&; else lcount&=lcount+1; hourout&= endxhour_ libraryIEEE; useIEEE.std_logic_1164. useieee.std_logic_unsigned. useieee.std_logic_arith. entityxalertis port( clk:inSTD_LOGIC; d_in:inSTD_LOGIC_VECTOR(6downto0); speak:outSTD_LOGIC; d_out:outSTD_LOGIC_VECTOR(2downto0) ); architecturexalert_archofxalertis typestateis(s1,s2,s3,s4); signalnext_state,current_state: begin --&& process(clk,current_state,d_in) begin ifd_in/=&0000000&then speak&='0'; next_state&=s1; current_state&=s1; d_out&=&000&; else ifclk='1'andclk'eventthen speak&='1'; current_state&=next_ casecurrent_stateis whens1=& d_out&=&000&; next_state&=s2; whens2=& d_out&=&001&; next_state&=s3; whens3=& d_out&=&010&; next_state&=s4; whens4=& d_out&=&100&; next_state&=s1; whenothers=& d_out&=&000&; endxalert_ libraryIEEE; useIEEE.std_logic_1164. useieee.std_logic_unsigned. useieee.std_logic_arith. entityxsettimeis port( hour:inSTD_LOGIC_VECTOR(5downto0); min:inSTD_LOGIC_VECTOR(6downto0); sec:inSTD_LOGIC_VECTOR(6downto0); reset:inSTD_LOGIC; clk:inSTD_LOGIC; sel:outSTD_LOGIC_VECTOR(2downto0); d_out:outSTD_LOGIC_VECTOR(3downto0) ); architecturexsettime_archofxsettimeis signalsel1:std_logic_vector(2downto0); begin --&& process(clk,reset,sel1,hour,min,sec) begin ifreset='0'then sel&=&000&; d_out&=&0000&; sel1&=&000&; else if(clk='1'andclk'event)then ifsel1&5then sel1&=sel1+1; else sel1&=&000&; sel&=sel1; casesel1is when&000&=& d_out(3)&='0'; d_out(2)&='0'; d_out(1)&=hour(5); d_out(0)&=hour(4); when&001&=& d_out&=hour(3downto0); when&010&=& d_out(3)&='0'; d_out(2)&=min(6); d_out(1)&=min(5); d_out(0)&=min(4); when&011&=& d_out&=min(3downto0); when&100&=& d_out(3)&='0'; d_out(2)&=sec(6); d_out(1)&=sec(5); d_out(0)&=sec(4); when&101&=& d_out&=sec(3downto0); whenothers=& endxsettime_ libraryIEEE; useIEEE.std_logic_1164. entityxdeledis port( d_in:inSTD_LOGIC_VECTOR(3downto0); a:outSTD_LOGIC; b:outSTD_LOGIC; c:outSTD_LOGIC; d:outSTD_LOGIC; e:outSTD_LOGIC; f:outSTD_LOGIC; g:outSTD_LOGIC ); 才五分啊,太少了吧。C语言的浮点数运算,fab(f1-f2) & 1e-7,指数最大可以写多少? - 知乎有问题,上知乎。知乎作为中文互联网最大的知识分享平台,以「知识连接一切」为愿景,致力于构建一个人人都可以便捷接入的知识分享网络,让人们便捷地与世界分享知识、经验和见解,发现更大的世界。0被浏览295分享邀请回答赞同 7 条评论分享收藏感谢收起写回答C语言中,怎么定义单片机的寄存器
按时间排序
位地址在汇编语言中,只能直接寻址,不支持间接寻址。那么,在 C 语言中,也就不能用指针来操作。所以不能定义单片机的寄存器。访问寄存器可以通过直接地址引用来完成。例如52单片机的寄存器有4组,分别为00H-07H,08H-0FH,10H-17H,18H-1FH,各组均8字节,要结合程序状态字寄存器PSW(D0H)中的RS0,RS1的组合来确定是哪一组。可以定义一个访问Rn的函数typedefuchar dacRn(uchar n)
//n=[0..7]{
uchar data *p;
n += (PSW & 0x18);
//PSW
7:CY 6:AC 5:F0 4:RS1 3:RS0 2:OV 1:F1 0:P//本来要右移三位变为0-3,但由于是8个一组要乘以8(左移3位),所以直接加上寄存器编号就可以了
return *(uchar data *)n;}
到厂家的网站上下载相关的数据手册。所有的信息在数据手册中都有。
#define reg_name
//前面定义寄存器名称..........#define name((pointer_type *) reg_name )//后面变成指针方便使用根据需要看是否需要加volatile~~~还要看你用什么样的编译器~~~
请看,一样的引脚。
你要干嘛 ?go 0080mov XXXX
如果你的端口是可以使用位寻址的话,头文件里面就有定义成结构体的,你看看就知道了
您好,就直接用if (P_^_==0) ……这里的_表示数字,51有四个端口,各有八个,你随便用。要用MAX232经过电平的转换,将TTL电平转化成232电平,才能与上位机(电脑)通信啊;然后用单片机的串行通信功能写个程序直接发就行了。SBUF=51里与串口发送的实际只一句,它就把temp传到SBUF然后再一位一位的串行发送了呀,至于它是怎么发的,我们没必要知道啊;那是串行通信的协议;比如吧,sbit shu=P2^0;if (shu==0 )
SBUF=0;它就把0这个数据发到上位机。
如果 P1是可以位寻址的话,定义另一个位变量来保存P1口的值,通过比较此变量与P1口的值来判断电平有没有变化。if(pbak!=P1){
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请输入私信内容:按键精灵 基本命令中的 键盘ASCII码 a-z 1-0 F1-F12详细的进C语言高手解答_百度知道
按键精灵 基本命令中的 键盘ASCII码 a-z 1-0 F1-F12详细的进C语言高手解答
我最近在看按键精灵教程 键盘ASCII码 代码详细解释比如
键盘的 1代码是97
1-0 a-z F1-F12 空格 回车 键盘所有键的代码和鼠标 左右键 麻烦高手介绍下分不多诚意在绝不 关闭或者不给
另外按键格式是不是 格式: KeyPress [91] [12]
按0这个键12次 是这么写么...
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A 键到 Z 键与其 ASCII 码的相应值 'A ' 到 'Z ' 是一致的 常数 值 描述 vbKeyA 65 A 键 vbKeyB 66 B 键 vbKeyC 67 C 键 vbKeyD 68 D 键 vbKeyE 69 E 键 vbKeyF 70 F 键 vbKeyG 71 G 键 vbKeyH 72 H 键 vbKeyI 73 I 键 vbKeyJ 74 J 键 vbKeyK 75 K 键 vbKeyL 76 L 键 vbKeyM 77 M 键 vbKeyN 78 N 键 vbKeyO 79 O 键 vbKeyP 80 P 键 vbKeyQ 81 Q 键 vbKeyR 82 R 键 vbKeyS 83 S 键 vbKeyT 84 T 键 vbKeyU 85 U 键 vbKeyV 86 V 键 vbKeyW 87 W 键 vbKeyX 88 X 键 vbKeyY 89 Y 键 vbKeyZ 90 Z 键 0 键到 9 键与其 ASCII 码的相应值 '0 ' 到 '9 ' 是一致的 常数 值 描述 vbKey0 48 0 键 vbKey1 49 1 键 vbKey2 50 2 键 vbKey3 51 3 键 vbKey4 52 4 键 vbKey5 53 5 键 vbKey6 54 6 键 vbKey7 55 7 键 vbKey8 56 8 键 vbKey9 57 9 键 数字小键盘上的键 常数 值 描述 vbKeyNumpad0 96 0 键 vbKeyNumpad1 97 1 键 vbKeyNumpad2 98 2 键 vbKeyNumpad3 99 3 键 vbKeyNumpad4 100 4 键 vbKeyNumpad5 101 5 键 vbKeyNumpad6 102 6 键 vbKeyNumpad7 103 7 键 vbKeyNumpad8 104 8 键 vbKeyNumpad9 105 9 键 vbKeyMultiply 106 乘号 (*) 键 vbKeyAdd 107 加号 (+) 键 vbKeySeparator 108 ENTER 键(在数字小键盘上) vbKeySubtract 109 减号 (-) 键 vbKeyDecimal 110 小数点 (.) 键 vbKeyDivide 111 除号 (/) 键 功能键 常数 值 描述 vbKeyF1 112 F1 键 vbKeyF2 113 F2 键 vbKeyF3 114 F3 键 vbKeyF4 115 F4 键 vbKeyF5 116 F5 键 vbKeyF6 117 F6 键 vbKeyF7 118 F7 键 vbKeyF8 119 F8 键 vbKeyF9 120 F9 键 vbKeyF10 121 F10 键 vbKeyF11 122 F11 键 vbKeyF12 123 F12 键 vbKeyF13 124 F13 键 vbKeyF14 125 F14 键 vbKeyF15 126 F15 键 vbKeyF16 127 F16 键
比如:想要按a键一次。按键精灵7 :KeyPress 65,1
按键精灵8:KeyPress “a”,1
采纳率:55%
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数字时钟的C语言程序,急求
系统由单片机、LED数码管、数字按键和功能按键等部分构成,能实现时间的调整和显示输出等功能。功能按键有两个SB0和SB1。SB0为时间设定键,按SB0后按0~9数字键就能设置时间。SB1为运行键,按下后,时间设置结束且时钟开始正常运行。由4个数码管显示时间,其中两个显示小时,两个显示分钟。24小时制
jueyehuanneng的答复:
设计原理 计数时钟由模为60的秒计数器模块、模为60的分计数模块、模为24的小时计数器模块、指示灯与报警器的模块、分/小时设定模块及输出显示模块等组成。通过&多功能复用按键F1-F12&信号接线组&F1_12(T)&的F9~F12的任意引线插孔可设置小时和分钟的值,并具有整点报时的功能。&br/&&br/& 输入信号:SETMIN为分钟设置信号;SETHOUR为小时设置信号;RESET为全局复位信号;CLK为全局时钟信号;CKDSP为数码管动态扫描信号。&br/&&br/& 拨码开关SW1~SW7内部已连接并已锁定,无需外接连线。&br/&&br/& 参考源程序 library IEEE; use IEEE.std_logic_1164. use ieee.std_logic_unsigned. use ieee.std_logic_arith. entity xsecond is port ( clk: in STD_LOGIC; clkset: in STD_LOGIC; setmin: in STD_LOGIC; reset: in STD_LOGIC; secout: out STD_LOGIC_VECTOR (6 downto 0); enmin: out STD_LOGIC ); architecture xsecond_arch of xsecond is signal sec : std_logic_vector(6 downto 0); signal emin : std_ signal sec1 : std_ begin -- && process(reset,sec,emin,setmin,clkset) begin if reset='0' then enmin&='0'; secout&=&0000000&; sec1&='1'; else sec1&='0'; secout&= if clkset='1' and clkset'event then if setmin='0' then enmin&='1'; else enmin&= process(clk,sec1) alias lcount : std_logic_vector(3 downto 0) is sec(3 downto 0); alias hcount : std_logic_vector(2 downto 0) is sec(6 downto 4); begin if sec1='1' then sec&=&0000000&; else if (clk='1' and clk'event) then if lcount=9 then lcount&=&0000&; if hcount/=5 then hcount&=hcount+1; emin&='0'; else hcount&=&000&; emin&='1'; else lcount&=lcount+1; emin&='0'; end xsecond_ library IEEE; use IEEE.std_logic_1164. use ieee.std_logic_unsigned. use ieee.std_logic_arith. entity xminute is port ( clkmin: in STD_LOGIC; reset: in STD_LOGIC; sethour: in STD_LOGIC; clk: in STD_LOGIC; minout: out STD_LOGIC_VECTOR (6 downto 0); enhour: out STD_LOGIC ); architecture xminute_arch of xminute is signal min : std_logic_vector(6 downto 0); signal ehour : std_ signal min1 : std_ begin -- && process(reset,clk,sethour,min,ehour) begin if reset='0' then enhour&='0'; minout&=&0000000&; min1&='0'; else min1&='1'; minout&= if clk='1' and clk'event then if sethour='0' then enhour&='1'; else enhour&= process(clkmin,min1) alias lcountm : std_logic_vector(3 downto 0) is min(3 downto 0); alias hcountm : std_logic_vector(2 downto 0) is min(6 downto 4); begin if min1='0' then min&=&0000000&; else if (clkmin='1' and clkmin'event) then if lcountm=9 then lcountm&=&0000&; if hcountm/=5 then hcountm&=hcountm+1; ehour&='0'; else hcountm&=&000&; ehour&='1'; else lcountm&=lcountm+1; ehour&='0'; end xminute_ library IEEE; use IEEE.std_logic_1164. use ieee.std_logic_unsigned. use ieee.std_logic_arith. entity xhour is port ( clkhour: in STD_LOGIC; reset: in STD_LOGIC; hourout: out STD_LOGIC_VECTOR (5 downto 0) ); architecture xhour_arch of xhour is signal hour : std_logic_vector(5 downto 0); begin -- && process(reset,clkhour,hour) alias lcount : std_logic_vector(3 downto 0) is hour(3 downto 0); alias hcount : std_logic_vector(1 downto 0) is hour(5 downto 4); begin if reset='0' then hourout&=&000000&; hour&=&000000&; else if (clkhour='1' and clkhour'event) then if lcount=9 then lcount&=&0000&; hcount&=hcount+1; else if hour=&100011& then hour&=&000000&; else lcount&=lcount+1; hourout&= end xhour_ library IEEE; use IEEE.std_logic_1164. use ieee.std_logic_unsigned. use ieee.std_logic_arith. entity xalert is port ( clk: in STD_LOGIC; d_in: in STD_LOGIC_VECTOR (6 downto 0); speak: out STD_LOGIC; d_out: out STD_LOGIC_VECTOR (2 downto 0) ); architecture xalert_arch of xalert is type state is (s1,s2,s3,s4); signal next_state,current_state : begin -- && process(clk,current_state,d_in) begin if d_in/=&0000000& then speak&='0'; next_state&=s1; current_state&=s1; d_out&=&000&; else if clk='1' and clk'event then speak&='1'; current_state&=next_ case current_state is when s1 =& d_out&=&000&; next_state&=s2; when s2 =& d_out&=&001&; next_state&=s3; when s3 =& d_out&=&010&; next_state&=s4; when s4 =& d_out&=&100&; next_state&=s1; when others =& d_out&=&000&; end xalert_ library IEEE; use IEEE.std_logic_1164. use ieee.std_logic_unsigned. use ieee.std_logic_arith. entity xsettime is port ( hour: in STD_LOGIC_VECTOR (5 downto 0); min: in STD_LOGIC_VECTOR (6 downto 0); sec: in STD_LOGIC_VECTOR (6 downto 0); reset: in STD_LOGIC; clk: in STD_LOGIC; sel: out STD_LOGIC_VECTOR (2 downto 0); d_out: out STD_LOGIC_VECTOR (3 downto 0) ); architecture xsettime_arch of xsettime is signal sel1 : std_logic_vector(2 downto 0); begin -- && process(clk,reset,sel1,hour,min,sec) begin if reset='0' then sel&=&000&; d_out&=&0000&; sel1&=&000&; else if (clk='1' and clk'event) then if sel1&5 then sel1&=sel1+1; else sel1&=&000&; sel&=sel1; case sel1 is when &000& =& d_out(3)&='0'; d_out(2)&='0'; d_out(1)&=hour(5); d_out(0)&=hour(4); when &001& =& d_out&=hour(3 downto 0); when &010& =& d_out(3)&='0'; d_out(2)&=min(6); d_out(1)&=min(5); d_out(0)&=min(4); when &011& =& d_out&=min(3 downto 0); when &100& =& d_out(3)&='0'; d_out(2)&=sec(6); d_out(1)&=sec(5); d_out(0)&=sec(4); when &101& =& d_out&=sec(3 downto 0); when others =& end xsettime_ library IEEE; use IEEE.std_logic_1164. entity xdeled is port ( d_in: in STD_LOGIC_VECTOR (3 downto 0); a: out STD_LOGIC; b: out STD_LOGIC; c: out STD_LOGIC; d: out STD_LOGIC; e: out STD_LOGIC; f: out STD_LOGIC; g: out STD_LOGIC ); 才五分啊,太少了吧。