NiosⅡ_百度百科
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Nios Ⅱ是公司推出的采用、具有32位指令集的第二代片上可编程的, 其最大优势和特点是模块化的硬件结构, 以及由此带来的灵活性和可裁减性。
NiosⅡ综述
相对于传统的处理器, Nios Ⅱ系统可以在设计阶段根据实际的需求来增减外设的数量和种类。设计者可以使用ALTERA 提供的开发工具SOPC Builder, 在FPGA(现场可编程逻辑门阵列)器件上创建软硬件开发的基础平台, 也即用SOPC Builder创建软核CPU和参数化的接口总线Avalon。在此基础上, 可以很快地将(包括处理器、、和用户逻辑电路)与常规软件集成在单一可编程芯片中。而且, SOPC Builder还提供了标准的,以便用户将自己的外围电路做成Nios Ⅱ可以添加的外设模块。这种设计方式, 更加方便了各类系统的调试。
NiosⅡ分类
Nios II系列包括3种产品，分别是：Nios II/f（快速）——最高的系统性能，中等FPGA使用量；Nios II/s（标准）——高性能，低FPGA使用量；Nios II/e(经济)——低性能，最低的FPGA使用量。这3种产品具有32位处理器的基本结构单元——32位指令大小，32位数据和地址路径，32位和32个源；使用同样的（ISA），100%兼容，设计者可以根据系统需求的变化更改CPU，选择满足性能和成本的最佳方案，而不会影响已有的软件投入。
NiosⅡ特点
Nios II系列支持使用专用指令。专用指令是用户增加的硬件模块，它增加了（ALU）。用户能为系统中使用的每个Nios II处理器创建多达256个专用指令，这使得设计者能够细致地调整系统硬件以满足性能目标。专用指令逻辑和本身Nios II指令相同，能够从多达两个源取值，可选择将结果写回目标寄存器。同时，Nios II系列支持60多个外设选项，开发者能够选择合适的外设，获得最合适的处理器、外设和接口组合，而不必支付根本不使用的硅片功能。　Nios II系列能够满足任何应用32位的需要，客户可以将第一代Nios处理器设计移植到某种Nios II处理器上，Altera将长期支持现有FPGA系列上的第一代Nios处理器。另外，Altera提供了一键式移植选项，可以升级至Nios II系列。Nios II处理器也能够在HardCopy器件中实现，Altera还为基于Nios II处理器的系统提供ASIC的移植方式。
NiosⅡ开发环境
Nios II处理器具有完善的软件开发套件，包括编译器、（IDE）、JTAG调试器、（RTOS）和TCP/IP协议栈。设计者能够用Altera Quartus II开发软件中的SOPC Builder系统开发工具很容易地创建专用的处理器系统，并能够根据系统的需求添加Nios II处理器核的数量。
使用Nios II能够为Nios II系统构建软件，即一键式自动生成适用于系统硬件的专用C/C++运行环境。Nios II集成开发环境（IDE）提供了许多软件模板，简化了项目设置。此外，Nios II开发套件包括两个第三方（RTOS）——MicroC/OS-II(Micrium)，Nucleus Plus(ATI/Mentor)以及供网络应用使用的TCP/IP协议栈。
NiosⅡ总结
长期以来，Altera一直推行战略的原因是，随着应用的ASIC开发日益受到成本的困扰，OEM日渐转向FPGA来构建自己的系统。这些系统中绝大多数需要一个处理器，而Altera正是为设计者提供了为FPGA优化的灵活的嵌入式处理器方案，可以满足16位和32位嵌入式处理器市场的需求。估计到2007年，该市场价值将到达110亿美元。From Wikipedia, the free encyclopedia
For other uses of "NIOS", see .
Nios II is a 32-bit embedded-processor architecture designed specifically for the
family of . Nios II incorporates many enhancements over the original Nios architecture, making it more suitable for a wider range of embedded computing applications, from
to system-control.
Nios II is comparable to , a competing softcore CPU for the
family of FPGA. Unlike Microblaze, Nios II is licensable for standard-cell
through a third-party IP provider,
Designware. Through the Designware license, designers can port Nios-based designs from an FPGA-platform to a mass production ASIC-device.
Nios II is a successor to Altera's first configurable 16-bit embedded processor .
Like the original Nios, the Nios II architecture is a
architecture which is implemented entirely in the programmable logic and memory blocks of Altera FPGAs. The soft-core nature of the Nios II processor lets the system designer specify and generate a custom Nios II core, tailored for his or her specific application requirements. System designers can extend the Nios II's basic functionality by adding a predefined memory management unit, or defining custom instructions and custom peripherals.
Similar to native Nios II instructions, user-defined instructions accept values from up to two 32- source registers and optionally write back a result to a 32-bit destination register. By using custom instructions, the system designers can fine-tune the system hardware to meet performance goals and also the designer can easily handle the instruction as a macro in .
For performance-critical systems that spend most CPU cycles executing a specific section of code, a user-defined peripheral can potentially offload part or all of the execution of a software-algorithm to user-defined , improving power-efficiency or application throughput.
Introduced with Quartus 8.0, the optional MMU enables Nios II to run operating systems which require hardware-based paging and protection, such as the Linux kernel. Without an MMU, Nios is restricted to operating systems which use a simplified protection and virtual memory-model: e.g.,
Introduced with Quartus 8.0, the optional MPU provides memory protection similar to that provided by an MMU but with a simpler programming model and without the performance overhead associated with an MMU.
Nios II classic is offered in 3 different configurations: Nios II/f (fast), Nios II/s (standard), and Nios II/e (economy). Nios II gen2 is offered in 2 different configurations: Nios II/f (fast), and Nios II/e (economy).
The Nios II/f core is designed for maximum performance at the expense of core size. Features of Nios II/f include:
Separate instruction and data caches (512
Access to up to 2
of external address space
Optional tightly coupled memory for instructions and data
Six-stage pipeline to achieve maximum /MHz
Single-cycle hardware multiply and barrel shifter
Optional hardware divide option
Dynamic branch prediction
Up to 256 custom instructions and unlimited hardware accelerators
debug module
Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace
Nios II/s core is designed to maintain a balance between performance and cost. Features of Nios II/s include:
Instruction cache
Up to 2 GB of external address space
Optional tightly coupled memory for instructions
Five-stage pipeline
Static branch prediction
Hardware multiply, divide, and shift options
Up to 256 custom instructions
debug module
Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace
The Nios II/e core is designed for smallest possible logic utilization of FPGAs. This is especially efficient for low-cost Cyclone II FPGA applications. Features of Nios II/e include:
Up to 2 GB of external address space
debug module
Complete systems in fewer than 700
Optional debug enhancements
Up to 256 custom instructions
Free, no license required
Nios II uses the Avalon switch fabric as the interface to its embedded peripherals. Compared to a traditional bus in a processor-based system, which lets only one bus master access the bus at a time, the Avalon switch fabric, using a slave-side arbitration scheme, lets multiple masters operate simultaneously.
Development for Nios II consists of two separate steps: hardware generation, and software creation.
Development is hosted inside an Altera application called the Embedded Design Suite (EDS). The EDS contains a complete integrated development environment to manage both hardware and software in two separate steps:
Nios II hardware designers use the Qsys system integration tool, a component of the Quartus-II package, to configure and generate a Nios system. The configuration
(GUI) allows users to choose the Nios-II's feature-set, and to add peripheral and I/O-blocks (timers, memory-controllers, serial interface, etc.) to the embedded system. When the hardware specification is complete, Quartus-II performs the synthesis, place & route to implement the entire system on the selected FPGA target.
Qsys is replacing the older SOPC (System-on-a-Programmable-Chip) Builder, which could also be used to build a Nios II system, and is being recommended for new projects.
A separate package, called the Embedded Design Suite (EDS), manages the software development. Based on the
IDE, the EDS includes a C/C++ compiler (based on the ), debugger, and an instruction-set simulator. EDS allows programmers to test their application in simulation, or download and run their compiled application on the actual FPGA host.
Because the C/C++ development-chain is based on GCC, the vast majority of
software for
compiles and runs with minimal or no modification. Third-party operating-systems have also been ported to Nios II. These include RTOS, Micrium , , ,
. Altera 2012.
real-time operating system
(RISC) processor architectures第一个NIOS II工程using Qsys-------Let Qsys Say Hello
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2.添加原理图文件
注：似乎Nios II工程都需要涉及到原理图编程。
3.进入Qsys进行内核设计
注：启动Qsys后，系统已经为内核默认添加了一个组件clk_0。
4.设置时钟名字和频率
注：开发板上的时钟输入为50MHz。
5.添加Nios II核
注：选择Nios II Core 为：Nios II/f，其他选项卡均保持默认设置。
6.进行时钟连接操作
7.添加On-Chip-Memory(RAM)核
注：同时，需要设定片上内存大小，在此，我们设定为40960，即40KB，其他选项卡均保持为默认设置。
8.进行时钟，数据端口，指令端口的连接
注：关于数据和指令端口的连线规则，如果是存储器这类的IP核，需要将其Slave端口同Nios II的data_master和instruction_master相连，而其他非存储器IP核则只需连接到Nios II的data_master即可。
9.添加System ID Peripheral核
注：输入32 bit System ID号。
10.进行时钟，数据端口的连接
注：由于System ID Peripheral不为存储器设备，挂载在Nios II上时，只需要与data_master相连，不需要与instruction_master相连。
11.添加JTAG UART核
注：保持默认设置即可。
12.进行时钟，数据端口的连接
注：由于JTAG UART不为存储器设备，挂载在Nios II上时，只需要与data_master相连，不需要与instruction_master相连。
13.指定Nios II的复位和异常地址
配置Nios II Processor的Reset Vetor和Exception Vector为onchip_ram.s1。
14.连接复位信号
点击Qsys主界面菜单栏中的“System”下的“Create Global Reset Network”。
15.进行基地址分配
点击Qsys主界面菜单栏中的“System”下的“Assign Base Addresses”。
16.进行中断号的分配
17.生成Qsys系统
点击Generate HDL。
18.将配置好的kernel添加到原理图文件中
19.将IP文件添加到工程当中
20.添加锁相环
注：需要输入芯片速度等级与输入频率参数。
21.管脚生成
选中单个symbol，点击鼠标反键，单击Generate Pins for symbol ports。
22.配置芯片
23.引脚分配
24.开启Eclipse
25.新建应用
File-New-Nios II Application and BSP from Template.
26.Build Project
27.运行程序
Run as ---- Nios II hardware
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迷上了代码！NIOS_II中FLASH的使用_NIOS_II中FLASH的使用免费下载_爱问共享资料
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NIOS_II中FLASH的使用.pdf
简介：NIOS II做嵌入式开发的资料，非常有用的哦！
NIOS_II中FLASH的使用.pdf
NIOS_II中FLASH的使用.pdf
简介：NIOS II做嵌入式开发的资料，非常有用的哦！
关于FLASH下载的资料
制作一个ip在Quartus_II和Nios_II中使用
在Nios II 处理器上使用MicroC-OS-II(英文).pdf
关于FLASH下载的资料
FPGA，NIOS资料
NIOS II 那些事儿，你懂得。
FPGA内嵌软核NiosII的使用教程，很详细哦。
NIOS II 那些事儿,传给想学nios II的朋友
教你如何用NIOS_ii，编写软核。
NIOS II做嵌入式开发的资料，非常有用的哦！
关于FPGA读写SDRAM的资料，非常有用的哦！
关于FPGA读写SDRAM的资料，非常有用的哦！
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