AD9984A Datasheet and Product Info | Analog Devices
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High Performance 10-Bit Display Interface
Manufactured by:
Data Sheet
Features and Benefits
10-bit, analog-to-digital converters
170 MSPS maximum conversion rate
Low PLL clock jitter at 170 MSPS
Automatic gain matching
Automated offset adjustment
2:1 input mux
Power-down via dedicated pin or serial register
4:4:4, 4:2:2, and DDR output format modes
Variable output drive strength
Odd/even field detection
External clock input
Regenerated Hsync output
Product Categories
Product Details
The AD9984A is a complete 10-bit, 170 MSPS, monolithic analog interface optimized for capturing YPbPr video and RGB graphics signals. Its 170 MSPS encode rate capability and full power analog bandwidth of 300 MHz support all HDTV video modes up to 1080p, as well as graphics resolutions up to UXGA (1600 × 1200 at 60 Hz).
The AD9984A includes a 170 MHz triple ADC with an internal reference, a PLL, and programmable gain, offset, and clamp control. The user provides only a 1.8 V power supply and an analog input. Three-state CMOS outputs can be powered from 1.8 V to 3.3 V.
The AD9984A on-chip PLL generates a sample clock from the tri-level sync (for YPbPr video) or the horizontal sync (for RGB graphics). Sample clock output frequencies range from 10 MHz to 170 MHz. With internal coast generation, the PLL maintains its output frequency in the absence of a sync input. A 32-step sampling clock phase adjustment is provided. Output data, sync, and clock phase relationships are maintained.
The auto-offset feature can be enabled to automatically restore the signal reference levels and calibrate out any offset differences between the three channels. The auto channel-to-channel gain-matching feature can be enabled to minimize any gain mismatches between the three channels.
The AD9984A also offers full sync processing for composite sync and sync-on-green applications. A clamp signal is generated internally or can be provided by the user through the CLAMP input pin.
Fabricated in an advanced CMOS process, the AD9984A is provided in a space-saving, Pb-free, 80-lead low profile quad flat package (LQFP) or 64-lead lead frame chip scale package (LFCSP) and is specified over the 0°C to 70°C temperature range.
Applications
Advanced TVs
Plasma display panels
RGB graphics processing
LCD monitors and projectors
Scan converters
Comparable Parts
Comparable Parts
Product Lifecycle
At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
Informational
Meeting Today's Digital Entertainment Challenges
Technical Articles
By Brett Li and Lie Dou, ATV Product Line, Analog Devices
(Digital TV DesignLine, 4/2/2008)
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AD9984AKCPZ-170 [详细内容]
10位模拟 - 数字转换器
转换率170 MSPS
170 MSPS的低抖动PLL时钟
自动增益匹配
自动偏移调整
2:1输入多路复用器
通过专用引脚或串行寄存器掉电
4:4:4，4:2:2，和DDR输出格式模式
可变输出驱动强度
奇/偶场检测
外部时钟输入
再生同步输出
可编程输出高阻抗控制
Hsyncs每垂直同步计数器
绿色同步（SOG）脉冲除尘器
等离子显示面板
RGB图形处理
LCD显示器和投影机
扫描转换器
AD9984A是一个完整的10位，170 MSPS，单片机，优化的捕捉YPbPr视频信号和RGB模拟接口图形信号。其170 MSPS编码速率和全功率模拟带宽为300 MHz，支持所有的HDTV视频
模式，以及1080p的图像分辨率可达UXGA（1600&1200 @60赫兹）。AD9984A包括一个170 MHz的三重ADC内部一个PLL，和可编程增益，偏移和钳参考，控制。用户只有1.8 V电源和模拟输入。三态CMOS输出可以采用1.8 V至3.3 V。AD9984A片上PLL生成一个采样时钟三电平同步（YPbPr视频）或水平同步（用于RGB图形）。采样时钟输出频率范围为10 MHz
至170 MHz。内部海岸一代，PLL保持其输出频率的情况下的同步输入。
深圳市科盛元电子科技有限公司
8& & 姜先生
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科盛元电子科技发展有限公司是一家专业的集成电路供应商，经过几年的发展，已经形成了以SILICON,NS,AD,TI产品为主、兼营世界各国半导体厂家，如：MAXIM、ST、INTEL、ON、AVAGO,ATMEL等，公司依托不断更新现货资源，服务于各大行业：图像声音处理，矩阵，仪器仪表、通信业、船舶工业、自动化控制、军用科研等高科技市场。在国内、国际主要半导体市场取得了长足的发展。
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android怎么解决应用程序与android设备多分辨率兼容问题？
要做到最好的话，只能A、通过代码获得当前设备分辨率，再设置B、写不同layout-320x240等等布局
尽量多用相对布局，这样不同分辨率大概可行
--- 共有 3 条评论 ---
我发现了中最简单的方法，将layout_width和layout_height设置成0px，利用layout_weight实现控件等比例缩放
布局文件向上兼容，尽量用低版本的布局文件就好了，为了更好的用户体验，只能多做工作了，不过你倒可以试试用dimen定义，再在代码里判断赋值
这样子确实可行，但是要为每种不同分辨率写相应的布局也太麻烦了吧，而且控件属性值和控件之间的间距也不好换算，还有就是每一个布局页面都要对应多个版本的layout，是不是很麻烦。。。。
这是个历史大难题
请看谷歌的安卓设计指南，上门说得很清楚。
这是一个很简单但是也很麻烦的问题。
--- 共有 1 条评论 ---
这是一个很简单同时也很没用的答案
在撰写布局的时候要使用RelativeLayout（相对布局），最外层布局的宽和高都是fill_parent，内部的其他控件都是使用padding属性，相对与最外层控件的内边距来设置。这样一般就能解决大部分的适配问题。
--- 共有 1 条评论 ---
嗯，安卓系统确实有一套自身自带的分辨率自适应功能，但是现在我要做到比较精确要在各种分辨率屏幕上都清晰的显示布局和图像啊AD9984AKCPZ-170 (AD) PDF技术资料下载
AD9984AKCPZ-170 供应信息 IC Datasheet 数据表 (1/44 页)
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AD9984AKCPZ-170
高性能10位显示器接口
[High Performance 10-Bit Display Interface]
&&AD9984AKCPZ-170PDF文件：
高性能10位显示器接口[High Performance 10-Bit Display Interface]
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&&&&AD [ ANALOG DEVICES ]
AD9984AKCPZ-170&&
AD9984AKCPZ-170&&
64-VFQFN 裸露焊盘，CSP&
AD9984AKCPZ-170&&
Pb-free 10-&
AD9984AKCPZ-170&&
High Performance10-Bit Display InterfaceAD9984AFEATURES10-bit, analog-to-digital converters170 MSPS maximum conversion rateLow PLL clock jitter at 170 MSPSAutomatic gain matchingAutomated offset adjustment2:1 input muxPower-down via dedicated pin or serial register4:4:4, 4:2:2, and DDR output format modesVariable output drive strengthOdd/even field detectionExternal clock inputRegenerated Hsync outputProgrammable output high impedance controlHsyncs per Vsync counterSync-on-green (SOG) pulse filterPb-free packageFUNCTIONAL BLOCK DIAGRAMAD9984A10AUTO OFFSETAUTO GAINPr/REDIN1Pr/REDIN02:1MUXCLAMP10PGA10-BITADCAUTO OFFSETAUTO GAINY/GREENIN1Y/GREENIN02:1MUXCLAMP10PGA10-BITADCAUTO OFFSETAUTO GAINPb/BLUEIN1Pb/BLUEIN02:1MUXCLAMPPGA10-BITADCOUTPUT DATA FORMATTER10Cb/Cr/REDOUT10Y/GREENOUT10Cb/BLUEOUTHSYNC1HSYNC02:1MUXDATACKSYNCPROCESSINGPLLSOGOUTODD/EVEN FIELDHSOUTVSOUT/A0VSYNC0VSYNC12:1MUXAPPLICATIONSAdvanced TVsPlasma display panelsLCDTVHDTVRGB graphics processingLCD monitors and projectorsScan convertersSOGIN1SOGIN0EXTCK/COASTCLAMPFILTSDASCL2:1MUXPOWERMANAGEMENTVOLTAGEREFSSERIAL REGISTERREFHIREFLOFigure 1.GENERAL DESCRIPTIONThe AD9984A is a complete 10-bit, 170 MSPS, monolithicanalog interface optimized for capturing YPbPr video and RGBgraphics signals. Its 170 MSPS encode rate capability and fullpower analog bandwidth of 300 MHz support all HDTV videomodes up to 1080p, as well as graphics resolutions up to UXGA(1600 × 1200 at 60 Hz).The AD9984A includes a 170 MHz triple ADC with an internalreference, a PLL, and programmable gain, offset, and clampcontrol. The user provides only a 1.8 V power supply and ananalog input. Three-state CMOS outputs can be powered from1.8 V to 3.3 V.The AD9984A on-chip PLL generates a sample clock from thetri-level sync (for YPbPr video) or the horizontal sync (for RGBgraphics). Sample clock output frequencies range from 10 MHzto 170 MHz. With internal coast generation, the PLL maintainsits output frequency in the absence of a sync input. A 32-stepsampling clock phase adjustment is provided. Output data,sync, and clock phase relationships are maintained.The auto-offset feature can be enabled to automatically restorethe signal reference levels and calibrate out any offset differencesbetween the three channels. The auto channel-to-channel gain-matching feature can be enabled to minimize any gainmismatches between the three channels.The AD9984A also offers full sync processing for composite syncand sync-on-green applications. A clamp signal is generatedinternally or can be provided by the user through the CLAMPinput pin.Fabricated in an advanced CMOS process, the AD9984A isprovided in a space-saving, Pb-free, 80-lead low profile quadflat package (LQFP) or 64-lead lead frame chip scale package(LFCSP) and is specified over the 0°C to 70°C temperature range.Rev. 0Information furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or otherrights of third parties that may result from its use. Specifications subject to change without notice. Nolicense is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and registered trademarks are the property of their respective owners.One Technology Way, P.O. Box 9106, Norwood, MA , U.S.A.Tel: 781.329.4700Fax: 781.461.3113(C)2007 Analog Devices, Inc. All rights reserved.